Very-Large-Scale Integration Physical Design
Engineering Change Order and Timing Design Rule Check| By: | Kim Ho Yeap, Ing Ming Tan |
| Publisher: | Cambridge Scholars Publishing |
| Print ISBN: | 9781036440534 |
| eText ISBN: | 9781036440541 |
| Edition: | 1 |
| Copyright: | 2025 |
| Format: | Page Fidelity |
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This book presents an innovative, automated approach to fix Timing-Design Rule Check (TDRC) violations in VLSI chip design. Using TCL scripting to streamline the Engineering Change Order (ECO) process, it achieves an 87% violation fix rate with minimal global timing shifts.